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2 a, low v in , low dropout linear regulator data sheet adp1740 / adp1741 rev. e document feedback information furnished by analog devic es is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s .a. tel: 781.329.4700 ? 2008 C 2013 analog devices, inc. all rights reserved. technical support www.analog .com features maximum output current: 2 a input voltage range: 1 . 6 v to 3. 6 v low shutdown current: 2 a low dropout voltage: 16 0 mv @ 2 a load initial accuracy: 1% accuracy over line, load, and temperature: 2 % 7 fixed output voltage options with s oft s tart : 0. 75 v to 2.5 v ( adp1740 ) adjust able output voltage option s with soft start : 0. 75 v to 3. 3 v ( adp1741 ) high psrr 6 5 db @ 1 k hz 6 5 db @ 10 k hz 5 4 db @ 100 k hz 23 v rms at 0.75 v output stable with small 4.7 f ceramic output capacitor excellent load and line transient response current - limit and thermal overload prot ection power - g ood indicator logic - controlled enable reverse c urrent p rotection applications server c omputers memory c omponents telecom munications equipment network equipment dsp/fpga/ microprocessor s upplies instrumentation equipment/data acquisition systems typical application circuits top view (not to scale) adp1740 1 2 3 4 vin vin 100k? 4.7f 4.7f v in = 1.8v v out = 1.5v vin en 12 11 10 9 vout vout vout sense 5 6 7 8 pg gnd ss nc pg 16 15 14 13 vin vin vout vout 10nf 07081-001 figure 1. adp1740 with fixed output volt age, 1.5 v top view (not to scale) adp1741 1 2 3 4 vin vin 100k? 4.7f 4.7f v in = 1.8v v out = 0.5v(1 + r1/r2) vin en 12 11 10 9 vout vout vout adj 5 6 7 8 pg gnd ss nc pg 16 15 14 13 vin vin vout vout 10nf r2 r1 07081-002 figure 2. adp174 1 with adjustable output voltage, 0. 75 v to 3.3 v general description the adp1740/adp1741 are low dropout (ldo) cmos linear regulators that operate from 1.6 v to 3.6 v and provide up to 2 a of outp ut current. these l ow v in / v out ldos are ideal for regu - lation of nanometer fpga geometries operating from 2.5 v down to 1.8 v i/o rails, and for powering core voltages down to 0.7 5 v . using an advanced , proprietary architecture, the adp1740/ adp1741 provid e high power supply rejection ratio (ps r r) and low noise, and achieve excellent line and load transient response with only a small 4.7 f ceramic output capacitor. the adp1740 is available in seven fixed output voltage options. the adp1741 is an adjustable vers ion that allows output voltages ranging from 0.75 v to 3.3 v via an external divider. the adp1740/adp1741 allow an external soft start capacitor to be connected to program the start up. a digital power - good output allows power system monitors to check the health of the output voltage. the adp1740/adp1741 are available in a 16 - lead, 4 mm 4 mm lfcsp, making them not only very compact solutions, but also providing excellent thermal performance for applica - tions that requir e up to 2 a of output current i n a small, low profile footprint.
adp1740/adp1741 data sheet rev. e | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical application circuits ............................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 input and output capacitor, recommended specifications .. 4 absolute maximum ratings ............................................................ 5 thermal data ................................................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ............................................. 7 t heory of operation ...................................................................... 11 soft start function ..................................................................... 11 adjustable output voltage (adp1741) ................................... 12 enable feature ............................................................................ 12 power - good feature .................................................................. 12 reverse current protection feature ........................................ 13 applications information .............................................................. 14 capacitor selection .................................................................... 14 undervoltage lockout ............................................................... 15 current - limit and thermal overload protection ................. 15 thermal considerations ............................................................ 15 pcb layo ut considerations ...................................................... 17 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision history 6 /1 3 rev. d to re v. e changed adjustable output voltage option with soft start (adp1755) from 0.75 v to 3. 0 v to 0.75 v to 3. 3 v (throughout) .................................................................................... 1 updated outline dimensions ....................................................... 19 12/12 rev. c to rev. d added junction temperature of 150 c , table 3 ........................... 5 changes to ordering guide .......................................................... 1 9 9 /1 2 rev. b to r ev. c changes to table 3 ............................................................................ 5 changes to ordering guide .......................................................... 19 2/10 rev. a to rev. b changes to table 4 ............................................................................ 5 changes to ordering guide .......................................................... 19 4/09 rev. 0 to rev. a changes to table 3 ............................................................................ 5 10/08 revision 0 : initial version
data sheet adp 1740/adp1741 rev. e | page 3 of 20 specifications v in = (v out + 0. 4 v) or 1.6 v (whichever is greater), i out = 1 0 0 ma , c in = c out = 4.7 f , t a = 25c , unless otherwise noted. table 1 . parameter symbol test conditions /comments min typ max unit input voltage range v in t j = ?40c to +125c 1 . 6 3. 6 v operating supply current 1 i gnd i out = 500 a 90 a i out = 100 ma 4 00 a i out = 100 ma, t j = ?40c to +125c 800 a i out = 2 a 1. 5 m a i out = 2 a, t j = ?40c to +125c 1.8 ma shutdown current i gnd - sd en = gnd , v in = 3.6 v 2 6 a en = gnd, v in = 1. 6 v, t j = ?40c to +85c 30 a en = gnd, v in = 3.6 v, t j = ?40c to +85c 100 a output voltage accuracy fixed output voltage accuracy (adp1740) v out i out = 100 ma ?1 +1 % i out = 1 0 ma to 2 a ?1.5 +1.5 % 1 0 ma < i o ut < 2 a, t j = ?40c to +125c ?2 +2 % adjustable output voltage accuracy (adp1741) 2 v adj i out = 100 ma 0.495 0.5 0.505 v i out = 1 0 ma to 2 a 0.492 0.508 v 10 ma < i out < 2 a, t j = ?40c to +125c 0.4 90 0.510 v line regulation ?v out /?v in v in = ( v out + 0.4 v) to 3.6 v , t j = ?40c to +125c ?0. 3 +0.3 %/v load regulation 3 ?v out /?i out i out = 10 ma to 2 a, t j = ?40c to +125c 0.5 %/a dropout voltage 4 v dropout i out = 100 ma, v out 1.8 v 10 mv i out = 100 ma, v out 1.8 v, t j = ?40c to +125 c 18 mv i out = 2 a, v out 1.8 v 160 mv i out = 2 a, v out 1.8 v, t j = ?40c to +125c 280 mv start - up time 5 t start - up c ss = 0 nf, i out = 10 ma 200 s c ss = 1 0 n f, i out = 10 ma 5.2 ms current - limit threshold 6 i limit 2.4 3 5 a thermal shutdown thermal shutdown threshold ts sd t j rising 150 c thermal shutdown hysteresis ts sd - hys 15 c pg output logic level pg output logic high pg high 1.6 v v in 3.6 v, i oh < 1 a 1.0 v pg output logic low pg low 1.6 v v in 3. 6 v, i ol < 2 ma 0.4 v pg ou tput delay from en t ransition , low to high 1.6 v v in 3.6 v, c ss = 10 nf 5.5 ms pg output threshold o utput v oltage f alling pg fal l 1.6 v v in 3.6 v ?10 % o utput v oltage r ising pg rise 1.6 v v in 3.6 v ? 6. 5 % en input en input logic high v ih 1.6 v v in 3.6 v 1.2 v en input logic low v il 1.6 v v in 3.6 v 0.4 v en input leakage current v i- leakage en = vin or gnd 0.1 1 a undervoltage lockout uvlo input voltage rising uvlo rise 1 .58 v input voltage falling uvlo fa ll 1.25 v hysteresis uvlo hys 1 0 0 mv soft start current i ss 1.6 v v in 3.6 v 0.6 0.9 1.2 a adj input bias current (adp1741) adj i- bias 1.6 v v in 3.6 v , t j = ?40c to +125c 1 0 150 na
adp1740/adp1741 data sheet rev. e | page 4 of 20 parameter symbol test conditions /comments min typ max unit sense input bias curr ent (adp1740 ) sns i- bias 1.6 v v in 3.6 v 10 a output noise out noise 10 hz to 100 khz, v out = 0.75 v 23 v rms 10 hz to 100 khz, v out = 2.5 v 6 5 v rms power supply rejection ratio psrr v in = v out + 1 v, i out = 10 ma 1 khz, v out = 0.75 v 6 5 db 1 khz, v out = 2.5 v 56 db 10 khz, v out = 0.75 v 6 5 db 10 khz, v out = 2.5 v 56 db 100 khz, v out = 0.75 v 5 4 db 100 khz, v out = 2.5 v 51 db 1 minimum output load current is 500 a. 2 accuracy when vout is connected directly to adj. when vout voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances of the resistors used . 3 based on an end point calculation using 10 ma and 2 a loads. see figure 6 for typical load regulation performance. 4 dropout voltage is defined as the input to outpu t voltage differential when the input voltage is set to the nominal output voltage. this applies only to output voltages above 1.6 v . 5 start - up time is defined as the time between the rising edge of en to v out being at 95% of its nominal value . 6 current - limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. for exampl e, the current limit for a 1.0 v output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 v, o r 0.9 v . input and output cap acitor, recommended specifications table 2 . parameter symbol test conditions /comments min typ max unit minimum input and output capacitance 1 c min t a = C 40c to +125c 3.3 f capacitor esr r esr t a = C 40c to +125c 0.001 0.1 ? 1 the minimum input and output capacitance should be greater than 3.3 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during capacitor selection to ensure that the minimum capacitance specification is met. x7r an d x5r type capacitors are recommended; y5v and z5u capacitors are not recommended for use with this ldo.
data sheet adp 1740/adp1741 rev. e | page 5 of 20 absolute maximum rat ings table 3 . parameter rating v in to gnd ? 0. 3 v to + 4 . 0 v v out to gnd ? 0. 3 v to v in en to gnd ? 0. 3 v to v in ss to gnd ? 0. 3 v to v in pg to gnd ? 0.3 v to + 4 . 0 v sense /adj to gnd ? 0.3 v to v in storage temperature range ? 65c to +150c junction temperature range ? 40c to +125c junction temperature 150 c soldering conditions jedec j - std -020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal data absolute maximum ratings apply only individually, not in combination. the adp 1740/adp1741 may be damaged when junction temperature limits are exceeded. monitoring ambient temperature does not guarantee that the junction tem perature is within the specified temperature limits. in applications with high power dissipation and poor pcb thermal resistance , the maximum ambient temperature may need to be derated. in applications with moderate power dissipation and low pcb thermal re sistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction temperature (t j ) of the device is dependent on the ambient temperature (t a ), the power dissipation of t he device (p d ) , and the junction - to - ambient thermal resistance of the package ( ja ). t j is calculated using the following formula : t j = t a + ( p d ja ) the j unction - to - ambient thermal resistance ( ja ) of the package is based on modeling and calculation usi ng a 4 - layer board. the junction - to - ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. the specified values of ja are based on a 4 - layer, 4 in 3 in circuit board. refer to jedec jesd 51- 7 for detailed information about board construction. for more information, see the a n - 772 application note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) , at www.analog.com . jb is the junction - to - board thermal characterization parameter with units of c/ w. jb of the package is based on modeling and calculation using a 4 - layer board. the jedec jesd51 - 12 document , guidelines for reporting and using electronic package thermal information , states that thermal characterization parameters are not the same as thermal resist ances. jb measures the component power flowing through multiple thermal paths rather than through a single path , as in thermal resistance ( jb ). therefore, jb thermal paths include convection from the top of the package , as well as radiation from the package, f actors that make jb more useful in real - world applications. maximum junction temperature (t j ) is calculated from the board temp er - ature (t b ) and the power dissipation (p d ) using the following formula: t j = t b + ( p d jb ) r efer to the jedec jesd51 - 8 and j esd51 - 12 documents for more detailed information about jb . thermal resistance ja and jb are specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 4 . thermal resis tance package type ja jb unit 16-l ead lfcsp with e xposed p ad 42 25. 5 c/w esd caution
adp1740/adp1741 data sheet rev. e | page 6 of 20 pin configuration s and function descrip tions pin 1 indicator 1 vin 2 vin 3 vin 4 en 11 vout 12 vout 10 vout 9 sense 5 pg 6 gnd 7 ss 8 nc 15 vin 16 vin 14 vout 13 vout top view (not to scale) adp1740 notes 1. nc = no connect. 2. the exposed pad on the bottom of the lfcsp enhances thermal performance and is electrically connected to gnd inside the package. it is recommended that the exposed pad be connected to the ground plane on the board. 07081-003 pin 1 indicator 1 vin 2 vin 3 vin 4 en 11 vout 12 vout 10 vout 9 adj 5 pg 6 gnd 7 ss 8 nc 15 vin 16 vin 14 vout 13 vout top view (not to scale) adp1741 notes 1. nc = no connect. 2. the exposed pad on the bottom of the lfcsp enhances thermal performance and is electrically connected to gnd inside the package. it is recommended that the exposed pad be connected to the ground plane on the board. 07081-004 figure 3 . adp1740 pin configuration figure 4 . adp1741 pi n configuration table 5 . pin function descriptions pin no. mnemonic description adp1740 adp1741 1, 2, 3, 15, 16 1, 2, 3, 15, 16 vin regulator input supply. bypass vin to gnd with a 4.7 f or greater capacitor. note that a ll fiv e vin pins must be connected to the source supply. 4 4 en enable input. drive en high to turn on the regulator; drive it low to turn off the regulator. for automatic startup, connect en to vin. 5 5 pg power - good output. this open - drain output requires an external pull - up resistor to vin. if the part is in shutdown mode , current - limit mode , or thermal shutdown, or if it falls below 90% of the nominal output voltage, the pg pin immediately transitions low. 6 6 gnd ground . 7 7 ss soft start pin . a capacito r connected to this pin determines the soft start time. 8 8 nc not c onnected. no internal connection . 9 sense sense input. this pin m easures the actual output voltage at the load and feeds it to the error amplifier. connect the sense pin as close to th e load as possible to minimize the effect of ir drop between the regulator output and the load. 9 adj adjust pin . a resistor divider from vout to adj sets the output voltage. 10, 11, 12, 13, 14 10, 11, 12, 13, 14 vout regulated output voltage. bypass v o ut to gnd with a 4.7 f or greater capacitor. note that a ll five vout pins must be connected to the load . ep ep exposed pad the e xposed pad on the bottom of the lfcsp enhances thermal performance and is electrically connected to gnd inside the package. it is recommended that the exposed pad be connect ed to the ground plane on the board.
data sheet adp 1740/adp1741 rev. e | page 7 of 20 typical performance characteristics v in = 1.9 v, v out = 1.5 v , i out = 100 ma, c in = c out = 4.7 f, t a = 25c, unless otherwise noted. 1.520 1.515 1.510 1.505 1.500 1.495 1.490 1.485 1.480 ?40 ?5 25 85 125 output voltage (v) junction temperature (c) 07081-005 load = 10ma load = 100ma load = 400ma load = 800ma load = 1.2a load = 2a figure 5. output voltage vs. junction temperature 1.520 1.515 1.505 1.495 1.510 1.500 1.490 1.485 1.480 10 100 1k 10k output voltage (v) load current (ma) 07081-006 figure 6. output voltage vs. load current 1.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 input voltage (v) load = 10ma load = 100ma load = 400ma load = 800ma load = 1.2a load = 2a 07081-007 1.520 1.515 1.510 1.505 1.500 1.495 1.490 1.485 1.480 output voltage (v) figure 7. output voltage vs. input voltage 1600 0 200 400 600 800 1000 1200 1400 ?40 ?5 25 85 125 ground current (a) junction temperature (c) load = 10ma load = 100ma load = 400ma load = 800ma load = 1.2a load = 2a 07081-008 figure 8. ground current vs. junction te mperature 1600 1400 1200 1000 800 600 400 200 0 10 100 1k 10k ground current (a) load current (ma) 07081-009 figure 9. ground current vs. load current 1600 1400 1200 1000 800 600 400 200 0 1.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 ground current (a) input voltage (v) load = 10ma load = 100ma load = 400ma load = 800ma load = 1.2a load = 2a 07081-010 figure 10 . ground current vs. input voltage
adp1740/adp1741 data sheet rev. e | page 8 of 20 100 90 70 80 60 50 40 30 20 10 0 ?40 85 60 35 10 ?15 shutdown current (a) temperature (c) 1.9v 2.0v 2.4v 2.6v 3.0v 3.6v 07081-011 figure 11 . shutdown current vs. temperature at various input voltages 0.25 0.20 0.15 0.10 0.05 0 1 10 100 1k 10k dropout voltage (v) load current (ma) 07081-012 1.6v 2.5v figure 12 . dropout voltage vs. load current, v out = 1.6 v, 2.5 v 2.50 2.35 2.45 2.40 2.30 2.25 2.20 2.15 2.10 2.3 2.5 2.7 2.4 2.6 2.8 output voltage (v) input voltage (v) load = 10ma load = 100ma load = 400ma load = 800ma load = 1.2a load = 2a 07081-013 figure 13 . output voltage vs. input voltage (in dropout) , v out = 2.5 v 4500 2500 4000 3500 3000 2000 1500 1000 500 0 2.3 2.5 2.7 2.4 2.6 2.8 ground current (a) input voltage (v) load = 10ma load = 100ma load = 400ma load = 800ma load = 1.2a load = 2a 07081-014 figure 14 . ground current vs. in put voltage (in dropout) , v out = 2.5 v ch1 1.0 a ? b w ch2 50mv b w m10s a ch1 380ma 1 2 t 10.40% t 07081-015 i load 1ma to 2a load step, 2.5a/s, 1a/div v out 50mv/div v in = 3.6v v out = 1.5v figure 15 . load transient response, c in = 4.7 f, c out = 4.7 f ch1 1.0 a ? b w ch2 50mv b w m10s a ch1 880ma 1 2 t 10.20% t 07081-016 i load 1ma to 2a load step, 2.5a/s, 1a/div v out 50mv/div v in = 3.6v v out = 1.5v figure 16 . load transient response, c in = 22 f, c out = 22 f
data sheet adp 1740/adp1741 rev. e | page 9 of 20 1 2 t 07081-017 ch1 500mv b w ch2 5mv b w m10s a ch4 800mv t 9.40% v in 3v to 3.5v input voltage step, 2v/s v out 5mv/div v out = 1.5v c in = c out = 4.7f figure 17 . line transient response , load current = 2 a 70 0 10 20 30 40 50 60 0.0001 0.001 0.01 0.1 1 10 noise (v rms) load current (a) 07081-018 0.75v 1.5v 2.5v figure 18 . noise vs. load current and output voltage 10 1 0.1 0.01 10 100 1k 10k 100k noise spectral density (v/ hz) frequency (hz) 07081-019 0.75v 1.5v 2.5v figure 19 . noise spectral density vs. output voltage, i load = 10 ma 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) load = 2a load = 1.2a load = 800ma load = 400ma load = 100ma load = 10ma 07081-020 figure 20 . power supply rejection ratio vs. frequency , v out = 0.75 v, v in = 1.75 v 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) 07081-021 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 load = 2a load = 1.2a load = 800ma load = 400ma load = 100ma load = 10ma figure 21 . power supply rejection ratio vs. frequency , v out = 1.5 v, v in = 2.5 v 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) 07081-022 l o ad = 2 a l o ad = 1 . 2 a l o ad = 800m a l o ad = 400m a l o ad = 100m a l o ad = 10m a figure 22 . power supply r ejection ratio vs. frequency, v out = 2.5 v, v in = 3.5 v
adp1740/adp1741 data sheet rev. e | page 10 of 20 0 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) 1.5v/2a 2.5v/10ma 0.75v/2a 2.5v/2a 0.75v/10ma 1.5v/10ma 07081-048 figure 23 . power supp ly rejection ratio vs. frequency and output voltage
data sheet adp 1740/adp1741 rev. e | page 11 of 20 theory of operation the adp1740 /adp1741 are low dropout linear regulators that u se an advanced, proprietary architecture to provide high power supply rejection ratio (psrr) and excellent line and load transien t response with only a small 4.7 f ceramic output cap ac - itor. both devices operate from a 1.6 v to 3.6 v input rail and provid e up to 2 a of output current. supply current in shut down mode is typically 2 a . uvlo vout vin sense ss short-circuit and thermal protection r1 0.5v ref r2 shutdown en pg gnd adp1740 reverse polarity protection pg detect 0.9a 07081-023 figure 24 . adp1740 internal block diagram uvlo vout vin adj ss short-circuit and thermal protection 0.5v ref shutdown en pg gnd adp1741 reverse polarity protection pg detect 0.9a 07081-024 figure 25 . adp1741 internal block diagram internally, the adp1740 /adp1741 cons ist of a reference, an error amplifier, a feedback voltage divider , and a pmos pass transistor. output current is delivered via the pmos pass transistor , which is controlled by the error amplifier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. if the feed - back voltage is lower than the reference voltage, the gate of the pmos device is pulled lower, allowing more current to pass an d increasing the output voltage. if the feedback voltage is higher than the reference voltage, the gate of the pmos device is pulled higher, allowing le ss current to pass and decreasing the output voltage. the adp1740 is available in seven fixed output voltage options from 0. 75 v to 2.5 v . the adp1740 a llows for connection of an external soft start capacitor, which controls the output voltage ramp during startup. the adp174 1 is an adjustable version with an output voltage that can be set to a value from 0. 75 v to 3. 3 v by an external voltage d ivider . bot h devices are controlled by an enable pin (en) . soft start functio n for applications that require a controlled startup, the adp1740 / adp1741 provide a programmable soft start function. the p rogrammable soft start is useful for reducing inrush current upon startup and for providing voltag e sequencing. to implement soft start, connect a small ceramic capacitor fro m ss to gnd. upon startup, a 0.9 a current source charges this capacitor. the adp1740 /adp1741 start - up output voltage is limited by the voltage at ss, providing a smooth ramp - up to the nominal output voltage. the soft start time is calculated as follows: t ss = v ref ( c ss / i ss ) (1) where : t ss is the soft start period. v ref is the 0. 5 v reference voltage . c ss is the soft start capacitance from ss to gn d . i ss is the current sourced from ss ( 0.9 a ). w hen the adp1740 /adp1741 are disabled (using the en pin ), the soft start capacitor is discharged to gnd through an internal 100 ? resistor. 2.50 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 0 2 4 6 8 10 voltage (v) time (ms) en 1nf 4.7nf 10nf 07081-025 figure 26 . v o ut ramp - up with external soft start capacitor
adp1740/adp1741 data sheet rev. e | page 12 of 20 ch1 2.0v b w ch2 500mv b w m40s a ch1 920mv 1 2 t 9.8% t 07081-026 en v out 500mv/div v out = 1.5v c in = c out = 4.7f figure 27 . v out ramp - up with internal soft start adjust able out put voltage ( adp1741 ) the output voltage of the adp1741 can be set over a 0. 7 5 v to 3. 3 v range. the output voltage is set by connecting a resistive voltage divider from v out to adj. the output voltage i s calcu - lated using the following equation : v out = 0. 5 v (1 + r1 / r2 ) (2) where : r1 is the resistor from v out to adj . r 2 is the resistor from adj to gnd. the max imum bias current into adj is 15 0 na, so to achieve less than 0.5 % error due to the bias current, use values less than 60 k for r2. enable feature the adp1740 /adp1741 use the en pin to enable and disable the v out pin s under normal operating conditions. as shown in figure 28, w hen a rising voltage on en crosses the active threshold, v out turns on. wh en a falling voltage on en crosses the inactive threshold, v out turns off . 2 ch1 500mv b w ch2 500mv b w m2.0ms a ch1 1.05v 1 t 29.6% t 07081-027 en v out 500mv/div v out = 1.5v c in = c out = 4.7f figure 28 . typical en pin operation as shown in figure 28 , the en pin has hysteresis built in. this hysteresis prevent s on/off o scillations that can o ccur due to noise on the en pin as it passes through the threshold points. the en pin active/inactive thresholds are derived from the v in voltage. therefore , these thresholds vary with changing input voltage . figure 29 shows typical en active/inactive thresholds when the input voltage varies from 1.6 v to 3. 6 v . 1.1 0.5 0.6 0.7 0.8 0.9 1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 en threshold (v) input voltage (v) en active en inactive 07081-028 figure 29 . typical en pin thresholds vs. input voltage power - g ood feature the adp1740/adp1741 provide a power - g ood pin , pg , to indicate the status of the output. this open - drain output requires an ex ternal pull - up resistor to vin . if the part is in shutdown mode , current - limit mode , or thermal shutdown, or if it falls below 9 0 % of the nominal output voltage, the power - g ood pi n (pg) immediately transitions low. during soft start, the rising threshold of the power - good signal is 93.5 % of t he nominal output voltage. the open - drain output is held low when the adp1740/ad p 1741 have sufficien t input voltage to turn on the internal pg transistor. an optional soft start delay can be detected. the pg transistor is terminated via a pull - up resistor to v out or v in . power - good accuracy is 93 .5 % of the nominal regulator output voltage when this voltage is rising, with a 90% trip point when this voltage is falling. regulator input voltage brownouts or glitches trigger power n o - g ood if v out falls below 90%. a normal power - down triggers p ower n o - g ood when v out drops below 9 0 % .
data sheet adp 1740/adp1741 rev. e | page 13 of 20 2 2 ch1 1.0v b w ch3 1.0v b w ch2 500mv b w m40.0s a ch3 900mv 1 t 50.40% t 07081-029 v in 1v/div v out 500mv/div pg 1v/div v out = 1.5v c in = c out = 4.7f figure 30 . typical pg b ehavior vs. v out , v in r ising (v out = 1.5 v) 2 2 ch1 1.0v b w ch3 1.0v b w ch2 500mv b w m40.0s a ch3 900mv 1 t 50.40% t 07081-030 v in 1v/div v out 500mv/div pg 1v/div v out = 1.5v c in = c out = 4.7f figure 31 . typical pg b ehavior vs. v out , v in falling (v out = 1.5 v) reverse current prot ection feature the adp1740/adp1741 have additional circuitry to protect against reverse current flow from vout to vin. for a typical ldo with a pmos pass device, there is an intrinsic body diode between vin and vout. when v in is greater than v out , this diode is reverse - biased. if v out is greater than v in , the intrinsic diode becomes forward - biased and conducts current from vout to vin, potentially causing destructive power dissipation. the reverse current protection circuitry detects when v out is greater than v in and reverses the direction of the intrinsic diode connection, rever se - biasing the diode. the gate of the pm os pass device is also connected to vout, keeping the device off. figure 32 shows a plot of the reverse current vs. the v out to v in differential. 4000 3500 3000 2500 2000 1500 1000 500 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 reverse current (a) v out ? v in (v) 07081-132 figure 32 . reverse current vs. v out ? v in
adp1740/adp1741 data sheet rev. e | page 14 of 20 application s information capacitor selection output capacitor the adp1740 /adp1741 are designed for operation with small, space - saving ceramic capacitors, but they function with most commonly used capacitors as long as care is taken with regard to the effective series resistance ( esr ) value. the esr of the output capaci tor affects the stabi lity of the ldo control loop . a minimum of 3.3 f capacitance with an esr of 1 00 m or less is recommended to ensure the stability of the adp1740 /adp1741 . t ransient response to changes in load current is also a ffected by output capacitance . using a larger value of output capacitance improve s the transient response of the adp1740 /adp174 1 to large changes in load current. figure 33 and figure 34 show the transient responses for o utput c apacitance values of 4.7 f and 22 f , respectively . 2 ch1 1.0a ? b w ch2 50.0mv b w m1.0s a ch1 380ma 1 t 10.80% t 07081-032 i load 1a/div 1ma to 2a load step, 2.5a/s v out 50mv/div v in = 3.6v, v out = 1.5v c in = c out = 4.7f figure 33 . output trans ient response, c out = 4.7 f 2 ch1 1.0a ? b w ch2 50.0mv b w m1.0s a ch1 880ma 1 t 11.80% t 07081-033 i load 1a/div 1ma to 2a load step, 2.5a/s v out 50mv/div v in = 3.6v, v out = 1.5v c in = c out = 22f figure 34 . output transient response, c out = 22 f input bypass capacitor connecting a 4.7 f capacitor from the v in pin to gnd reduces the circuit sensitivity to printed circuit board (pcb) layout, especially when long input traces or high source impedance are encountered. if output capacitance greater than 4.7 f is required, it is recommended that the input capacitor be increased to match it . input and output capacitor properties any good quality ceramic capacitors can be used with the adp1740 /adp1741 , as long as they meet the minimum capacitance and maximum esr requirements. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. c apacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions . x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended . y5v and z5u dielectrics are n ot recommended , due to their poor temperature and dc bias characteristics. figure 35 shows the capacitance vs. voltage bias characteristic s of an 0805 case, 4.7 f, 1 0 v, x5r capacitor. the voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. in general, a capacitor in a larger package or with a higher voltage rating exhibit s better stability. the temperature variation of the x5r dielectric is approximately 15% over the ? 40c to + 85c temperature range and is not a function of package size or voltage rating. 5 4 3 2 1 0 0 2 4 6 8 10 capacitance (f) voltage bias (v) murata p/n grm219r61a475ke34 07081-133 figure 35 . capacitance vs. voltage bias characteristic s use equation 3 to determine t he worst - case capacitance , accoun ting for capacitor variation over temperature, com - p onent tolerance, and voltage. c eff = c out (1 ? tempco ) (1 ? tol ) ( 3 ) where: c eff is the effective capacitance at the operating voltage. tempco is the worst - case capaci tor temperature coefficient. tol is the worst - case component tolerance .
data sheet adp1740/adp1741 rev. e | page 15 of 20 in this example, the worst - case temperature coefficient (tempco) over ? 40 c to +85 c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 1 0%, and c out = 4.46 f at 1.8 v , as shown in figure 35. substituting th ese values in equation 3 yields c eff = 4.46 f ( 1 ? 0. 15) ( 1 ? 0.1 ) = 3.41 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over temper - ature and tolerance at the chosen output voltage . to guarantee the performance of the adp17 40 /adp17 41, it is imperative that the effects of dc bias, temperature , and tolerances on the behavior of the capacitors be evalu ated for each application. undervoltage lockout the adp1 740/adp1741 have an internal undervoltage lockout circuit that disables all inputs and the output when the input volta ge is less than approximately 1.58 v. this ensures that the adp1 740/adp1741 inputs and the output behave in a predict - able manner during power - up. c urrent - l imit and t hermal overload protection the adp1740 /adp1741 are protected against damage due to excessive power dissipation by current - limit and thermal overload protection circuits . th e adp1740 / adp174 1 are designed to reach current limit when the output load reaches 3 a (typical). when the output load exceeds 3 a, the output voltage is reduced to maintain a constant current limit. thermal overload protection is included , which limit s t he junction temperature to a maximum of 150c (typical) . under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature begins to rise above 150c, the output is turned off , reduc ing the output current to z ero . when the junction temperature drops below 135c (typical) , t he output is turned on again and output current is restored to its nominal value . consider the case where a hard short from v out to ground occurs. at first , the adp1740 /adp1741 reach current limit so that only 3 a is conducted into the short. if sel f - heating of the junction becomes great enough to cause its temperature to rise above 150c , thermal shutdown activ ate s , turning off the output and reducing the output current to zero. as the juncti on temp er - ature cools and drops below 135c, the output turn s on and conduct s 3 a into the short, again caus ing the junction temper - ature to rise above 150c . this thermal oscillation between 135c and 150c cause s a current oscillation between 3 a and 0 a that continue s as long as the short remains at the output. current - limit and thermal overload protections are intended to protect the device against accidenta l overload conditions. for reliable operation, device power dissipation should be externally limi ted so that junction temperatures do not exceed 125c. thermal consideratio ns to guarantee reliable operation, the junction temperature of the adp1740 /adp1741 must not exceed 125c. to e nsure that the junction temperature stays below this maximum value, th e user needs to be aware of the parameters that contribute to junction temperature changes. thes e parameters include ambient tem - perature, power dissipation in the power device , and thermal resistance between the junction and ambient air ( ja ). the ja val ue is dependent on the package assembly compounds used and the amount of copper to which the gnd pin and the exposed pad (ep) of the package are soldered on the pcb . table 6 shows typical ja values for the 16- lead lfcsp for vario us pcb copper sizes. table 7 shows typical jb value s for the 16 - lead lfcsp . table 6 . typical ja values copper size ( mm 2 ) ja ( c/w), lfcsp 0 1 130 100 80 5 00 69 1000 54 640 0 42 1 device soldered to minimum size pin traces. table 7 . typical jb value s copper size (mm 2 ) jb (c/w) @ 1 w 100 32.7 500 31.5 1000 25.5 the junction temperature of the adp1740 /adp1741 can be calculated from the following equation: t j = t a + ( p d ja ) ( 4 ) w here : t a is the ambient temperature. p d is the power dissipation in the die, given by p d = [( v in ? v out ) i load ] + ( v in i gnd ) ( 5 ) where : v in and v out are the input and output voltages, respectively. i load is the load current. i gnd is the ground current . power dissipation due to ground current is quite small and can be ignored. therefore , the junction temperature equation can be simplified as follows : t j = t a + {[( v in ? v out ) i load ] ja } ( 6 ) as shown in equation 6 , for a given ambient tempera ture, input - to - output voltage differential, and continuous load current, a minimum copper size requirement exists for the pcb to ensure th at th e junction temperature does not rise above 125c. figure 36 through figure 41 show junction temperature calculations for different ambient temperatures, load currents, v in to v out d ifferential s, and areas of pcb copper.
adp1740/adp1741 data sheet rev. e | page 16 of 20 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 junction temperature, t j (c) v in ? v out (v) max junction temperature load = 10ma load = 100ma load = 250ma load = 500ma load = 1a load = 2a 07081-034 figure 36. 6400 mm 2 of pcb copper, t a = 25c, lfcsp 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 junction temperature, t j (c) v in ? v out (v) max junction temperature load = 10ma load = 100ma load = 250ma load = 500ma load = 1a load = 2a 07081-035 figure 37. 500 mm 2 of pcb copper, t a = 25c, lfcsp 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 junction temperature, t j (c) v in ? v out (v) max junction temperature load = 10ma load = 100ma load = 250ma load = 500ma load = 1a 07081-036 figure 38. 0 mm 2 of pcb copper, t a = 25c, lfcsp 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 junction temperature, t j (c) v in ? v out (v) max junction temperature load = 10ma load = 100ma load = 250ma load = 500ma load = 1a load = 2a 07081-037 figure 39. 6400 mm 2 of pcb copper, t a = 50c, lfcsp 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 junction temperature, t j (c) v in ? v out (v) max junction temperature load = 10ma load = 100ma load = 250ma load = 500ma load = 1a load = 2a 07081-038 figure 40. 500 mm 2 of pcb copper, t a = 50c, lfcsp 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 junction temperature, t j (c) v in ? v out (v) max junction temperature load = 10ma load = 100ma load = 250ma load = 500ma load = 1a 07081-039 figure 41. 0 mm 2 of pcb copper, t a = 50c, lfcsp
data sheet adp1740/adp1741 rev. e | page 17 of 20 in cases where the board temperature is known, the thermal characterization parameter, jb , can be used to estimate the junction temperature rise. maximum junction temperature (t j ) is calculated from the board temperature (t b ) and the power dissipation (p d ) using the following formula: t j = t b + ( p d jb ) (7) figure 42 through figure 45 show junction temperature calculations for different board temperatures, load currents, v in to v out differentials, and areas of pcb copper. 140 120 100 80 60 40 20 0 0.25 0.75 1.25 1.75 2.25 2.75 junction temperature, t j (c) v in ? v out (v) max junction temperature load = 10ma load = 100ma load = 250ma load = 500ma load = 1a load = 2a 07081-040 figure 42. 500 mm 2 of pcb copper, t b = 25c, lfcsp 140 120 100 80 60 40 20 0 0.25 0.75 1.25 1.75 2.25 2.75 junction temperature, t j (c) v in ? v out (v) max junction temperature load = 10ma load = 100ma load = 250ma load = 500ma load = 1a load = 2a 07081-041 figure 43. 500 mm 2 of pcb copper, t b = 50c, lfcsp 140 120 100 80 60 40 20 0 0.25 0.75 1.25 1.75 2.25 2.75 junction temperature, t j (c) v in ? v out (v) max junction temperature load = 10ma load = 250ma load = 500ma load = 1a load = 2a load = 100ma 07081-042 figure 44. 1000 mm 2 of pcb copper, t b = 25c, lfcsp 140 120 100 80 60 40 20 0 0.25 0.75 1.25 1.75 2.25 2.75 junction temperature, t j (c) v in ? v out (v) max junction temperature load = 10ma load = 250ma load = 500ma load = 1a load = 100ma 07081-043 load = 2a figure 45. 1000 mm 2 of pcb copper, t b = 50c, lfcsp pcb layout considerations heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the adp1740/ adp1741. however, as shown in table 6, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. here are a few general tips when designing pcbs: ? place the input capacitor as close as possible to the vin and gnd pins. ? place the output capacitor as close as possible to the vout and gnd pins. ? place the soft start capacitor close to the ss pin. ? connect the load as close as possible to the vout and sense pins (adp1740) or to the vout and adj pins (adp1741). use of 0603 or 0805 size capacitors and resistors achieves the smallest possible footprint solution on boards where area is limited.
adp1740/adp1741 data sheet rev. e | page 18 of 20 07081-044 figure 46 . evaluation board 07081-045 figure 47 . typical board layou t, top side 07081-046 figure 48 . typical board layout, bottom side
data sheet adp1740/adp1741 rev. e | page 19 of 20 outline dimensions 2 . 2 5 2 . 1 0 s q 1 . 9 5 compliant to jedec standards mo-220-vggc 02-26-2013-b 1 0.65 bsc p i n 1 i n d i c a t o r 1.95 ref 0.75 0.60 0.50 top view 12 max 0.80 max 0.65 typ seating plane coplanarity 0.08 1.00 0.85 0.80 0.35 0.30 0.25 0.05 max 0.02 nom 0.20 ref 16 5 13 8 9 12 4 0.60 max 0.60 max pin 1 indicator 4.10 4.00 sq 3.90 exposed pad for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.25 min bottom view 3.75 bsc sq figure 49. 16-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-16-4) dimensions shown in millimeters ordering guide model 1 temperature range output voltage (v ) package description package option adp1740acpz-0.75-r7 ?40c to +125c 0.75 16-lead lfcsp_vq cp-16-4 adp1740acpz-1.0-r7 ?40c to +125c 1.0 16-lead lfcsp_vq cp-16-4 adp1740acpz-1.1-r7 ?40c to +125c 1.1 16-lead lfcsp_vq cp-16-4 adp1740acpz-1.2-r7 ?40c to +125c 1.2 16-lead lfcsp_vq cp-16-4 adp1740acpz-1.5-r7 ?40c to +125c 1.5 16-lead lfcsp_vq cp-16-4 adp1740acpz-1.8-r7 ?40c to +125c 1.8 16-lead lfcsp_vq cp-16-4 adp1740acpz-2.5-r7 ?40c to +125c 2.5 16-lead lfcsp_vq cp-16-4 adp1741acpz-r7 ?40c to +125c adjustable, 0.75 to 3.3 16-lead lfcsp_vq cp-16-4 adp1740-1.5-evalz 1.5 evaluation board adp1741-evalz adjustable evaluation board 1 z = rohs compliant part.
adp1740/adp1741 data sheet rev. e | page 20 of 20 notes ? 2008 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07081 - 0 - 6/13(e)

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